Features for the TMS320C5505
- High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor
- 16.67-, 13.33-, 10-, 8.33-, 6.66-ns Instruction Cycle Time
- 60-, 75-, 100-, 120-, 150-MHz Clock Rate
- One/Two Instructions Executed per Cycle
- Dual Multipliers [Up to 200, 240, or 300 Million Multiply-Accumulates per Second (MMACS)]
- Two Arithmetic/Logic Units (ALUs)
- Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
- Software-Compatible With C55x Devices
- Industrial Temperature Devices Available
- 320K Bytes Zero-Wait State On-Chip RAM, Composed of:
- 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit
- 256K Bytes of Single-Access RAM (SARAM), 32 Blocks of 4K x 16-Bit
- 128K Bytes of Zero Wait-State On-Chip ROM
(4 Blocks of 16K x 16-Bit) - 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)
- 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:
- 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
- 8-/16-Bit NOR Flash
- Asynchronous Static RAM (SRAM)
- 16-bit SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
- Direct Memory Access (DMA) Controller
- Four DMA With 4 Channels Each (16-Channels Total)
- Three 32-Bit General-Purpose Timers
- One Selectable as a Watchdog and/or GP
- Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces
- Universal Asynchronous Receiver/Transmitter (UART)
- Serial-Port Interface (SPI) With Four Chip-Selects
- Master/Slave Inter-Integrated Circuit (I2C Bus™)
- Four Inter-IC Sound (I2S Bus™) for Data Transport
- Device USB Port With Integrated 2.0 High-Speed PHY that Supports:
- USB 2.0 Full- and High-Speed Device
- LCD Bridge With Asynchronous Interface
- Tightly-Coupled FFT Hardware Accelerator
- 10-Bit 4-Input Successive Approximation (SAR) ADC
- Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain and Power Supply
- Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB
- Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
- One integrated LDO (ANA_LDO) to power DSP PLL (VDDA_PLL) and 10-bit SAR ADC (VDDA_ANA)
- Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator
- On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM
- IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible - Up to 26 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions) - 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix)
- 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
- 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os
- 1.4-V Core (150 MHz), 1.8-V, 2.5-V, 2.75-V or 3.3-V I/Os