The DSP56002FC66 and the DSP56L002 are MPU-style general purpose Digital Signal Processors (DSPs), composed of an efficient 24-bit digital signal processor core, program and data memories, various peripherals, and support circuitry.
Memory
• On-chip Harvard architecture permitting simultaneous accesses to program and two data memories
• 512 × 24-bit on-chip program RAM and 64 × 24-bit bootstrap ROM
• Two 256 × 24-bit on-chip data RAMs
• Two 256 × 24-bit on-chip data ROMs containing sine, A-law and µ-law tables
• External memory expansion with 16-bit address and 24-bit data buses
• Bootstrap loading from external data bus, Host Interface, or Serial Communications Interface
Peripheral and Support Circuits
• Byte-wide Host Interface (HI) with direct memory access support
• Synchronous Serial Interface (SSI) to communicate with codecs and synchronous serial devices
— Up to 32 software-selectable time slots in network mode
• Serial Communication Interface (SCI) for full-duplex asynchronous communications
• 24-bit Timer/Event Counter also generates and measures digital waveforms
• On-chip peripheral registers memory mapped in data memory space
• Double buffered peripherals
• Up to 25 general purpose I/O (GPIO) pins
• Three external interrupt request pins; one non-maskable
• On-Chip Emulation (OnCE) port for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase-Locked Loop-based (PLL) frequency synthesizer for the core clock
• Power-saving Wait and Stop modes
• Fully static, HCMOS design for operating frequencies from 66 MHz or 40 MHz down to DC
• 132-pin Ceramic Pin Grid Array (PGA) package; 13 × 13 array
• 132-pin Plastic Quad Flat Pack (PQFP) surface-mount package; 24 × 24 × 4 mm
• 144-pin Thin Quad Flat Pack (TQFP) surface-mount package; 20 × 20 × 1.4 mm
• 3.3 V (DSP56L002) and 5 V (DSP56002) Power supply options
- Hersteller
- MOTOROLA
- Verpackung
- Tape & Reel (TR)/Cut Tape (CT)/Tray/Tube
- RoHs Status
- Lead free / RoHS Compliant
- Verpackung/Behälter
- QFP-132